http://www.quadibloc.com/arch/sriscint.htm

The RISC architecture contains several common elements. Some of them are no longer present in most chips that still call themselves RISC:

• All instructions execute in a single cycle.
• Floating-point operations, specifically, are therefore excluded.

But most of the defining characteristics of RISC do remain in force:

• All instructions occupy the same amount of space in memory.
• Only load, store, and jump instructions directly address memory. Calculations are performed only between operands in registers.

https://groups.google.com/g/comp.arch/c/IZP5KUJprHw?pli=1

MOST RISCs:
3a) Have 1 size of instruction in an instruction stream
3b) And that size is 4 bytes
3c) Have a handful (1-4) addressing modes) (* it is VERY hard to count these things; will discuss later).
3d) Have NO indirect addressing in any form (i.e., where you need one memory access to get the address of another operand in memory)
4a) Have NO operations that combine load/store with arithmetic, i.e., like add from memory, or add to memory. (note: this means especially avoiding operations that use the value of a load as input to an ALU operation, especially when that operation can cause an exception. Loads/stores with address modification can often be OK as they don’t have some of the bad effects)
4b) Have no more than 1 memory-addressed operand per instruction
5a) Do NOT support arbitrary alignment of data for loads/stores
5b) Use an MMU for a data address no more than once per instruction
6a) Have >=5 bits per integer register specifier
6b) Have >= 4 bits per FP register specifier

Note that none of this has to do with reducing the number of instructions, which is what people tend to think of when they hear the name.